LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY Project IS
    PORT (
        -- CLOCK
        ADC_CLK_10 : IN STD_LOGIC;
        MAX10_CLK1_50 : IN STD_LOGIC;
        MAX10_CLK2_50 : IN STD_LOGIC;
        -- SEG7
        HEX0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        HEX1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        HEX2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        HEX3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        HEX4 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        HEX5 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        -- KEY (debounced)
        KEY : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        -- LED
        LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
        -- SW
        SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0));
END Project;

ARCHITECTURE ProjectArch OF Project IS

BEGIN

END ProjectArch; -- ProjectArch